Baker, “The concurrent simulation of nearly identical digital networks,” Computer 7:39–44, April 1974. Armstrong, “A deductive method for simulating faults in logic circuits,” IEEE Trans. Seshu, “On an improved diagnosis program,” IEEE Trans. Agrawal, “LSI product quality and fault coverage,” 18th Design Automation Conf., June 1981, pp. The addition of alternative delay models is under development. Currently DSIM uses the zero-delay timing model. An implementation consists of only about 300 lines of “C” language statements added to the event-driven true-value simulator in an existing sequential circuit test generator program, STG3. In addition, owing to the simplicity of this algorithm, DSIM is very easy to implement and maintain. Experiments have shown that DSIM runs 3 to 12 times faster than an existing concurrent fault simulator. In this manner, DSIM is more efficient than serial fault simulation. Also, unlike serial fault simulation, DSIM simulates each machine by reprocessing its differences from the previously simulated machine. Therefore, DSIM dramatically reduces the memory requirement and the overhead in the memory management in concurrent fault simulation. Unlike concurrent fault simulation, for every test vector, DSIM simulates the good machine and each faulty machine separately, one after another, rather than simultaneously simulating all machines. A new fast fault simulation algorithm called differential fault simulation, DSIM, for synchronous sequential circuits is described.
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